DDR stands for double data rate. Physical DDR interfaces (PHYs) are implemented using accurate timing when various signals, such as clock, command, address, and data signals are each launched. Incoming signals are also delayed to be captured. In some existing approaches, delay lines are used to delay such signals. The delay lines are compensated against manufacturing process variation, supply voltage variation, and temperature (PVT) variation.
In high speed operations of the DDR PHYs, such as operations in the range of Giga-bits per second, delay locked loops are used to calibrate the delay lines. Different ways of calibration are used. For example, calibration is performed once when the circuit is initialized or is performed continuously during operations of the circuits when the signals drift during circuit operations. Further, when semiconductor chips that have DDR interfaces and related circuits are manufactured on a printed circuit board, board artifacts, such as trace length mismatches, are also compensated for.
In some applications, switching between high performance and low power modes involves changing operating frequencies. When operating frequencies of DDR interfaces change, delay locked loops relock to the new clock frequency and the operation of locking to the new clock frequency can take hundreds of clock cycles.